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?2001 silicon storage technology, inc. s71172-05-000 10/01 523 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. concurrent superflash and combomemory are trademarks of silicon storage technology, inc. these specifications are subject to change without notice. data sheet features: ? flash organization: 1m x16 dual-bank architecture for concurrent read/write operation ? 16 mbit: 12 mbit + 4 mbit sram organization: ? 2 mbit: 256k x8 or 128k x16 ? 4 mbit: 512k x8 or 256k x16 single 2.7-3.3v read and write operations superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention low power consumption: ? active current: 25 ma (typical) ? standby current: 20 a (typical) hardware sector protection (wp#) ? protects 4 outer most sectors (4 kword) in the larger bank by holding wp# low and unprotects by holding wp# high hardware reset pin (rst#) ? resets the internal state machine to reading data array sector-erase capability ? uniform 1 kword sectors block-erase capability ? uniform 32 kword blocks read access time ? flash: 70 and 90 ns ? sram: 70 and 90 ns latched address and data fast erase and word-program: ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 70 ms (typical) ? word-program time: 14 s (typical) ? chip rewrite time: 8 seconds (typical) automatic write timing ? internal v pp generation end-of-write detection ? toggle bit ? data# polling ? ready/busy# pin cmos i/o compatibility jedec standard command set conforms to common flash memory interface (cfi) packages available ? 56-ball lfbga (8mm x 10mm) product description the sst34hf1621/1641 combomemory devices inte- grate a 1m x16 cmos flash memory bank with a 256k x8/ 128k x16 or 512k x8/ 256k x16 cmos sram memory bank in a multi-chip package (mcp). these devices are fabricated using sst?s proprietary, high-performance cmos superflash technology incorporating the split-gate cell design and thick oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. the sst34hf1621/1641 devices are ideal for applications such as cellular phones, gpss, pdas and other portable electronic devices in a low power and small form factor system. the sst34hf1621/1641 features dual flash memory bank architecture allowing for concurrent operations between the two flash memory banks and the sram. the devices can read data from either bank while an erase or program operation is in progress in the opposite bank. the two flash memory banks are partitioned into 4 mbit and 12 mbit with top or bottom sector protection options for storing boot code, program code, configuration/parameter data and user data. the superflash technology prov ides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/program cycles. the sst34hf1621/1641 devices offer a guaranteed endurance of 10,000 cycles. data retention is rated at greater than 100 years. with high per- formance word-program, the flash memory banks provide a typical word-program time of 14 sec. the entire flash memory bank can be erased and programmed word-by- word in typically 8 seconds for the sst34hf1621/1641, when using interface features such as toggle bit or data# polling to indicate the completion of program operation. to protect against inadvertent flash write, the sst34hf1621/ 1641 devices contain on-chip hardware and software data protection schemes. 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 sst34hf1621/ 164116 mb csf (x16) + 2/4 mb sram (x16) combomemories
2 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 the flash and sram operate as two independent memory banks with respective bank enable signals. the memory bank selection is done by two bank enable signals. the sram bank enable signal, bes1# and bes2, selects the sram bank. the flash memory bank enable signal, bef#, has to be used with software data protection (sdp) com- mand sequence when controlling the erase and program operations in the flash memory bank. the memory banks are superimposed in the same memory address space where they share common address lines, data lines, we# and oe# which minimize power consumption and area. bus contention is eliminated as the device will not recog- nize both bank enables as being simultaneously active. designed, manufactured, and tested for applications requir- ing low power and small form factor, the sst34hf1621/ 1641 are offered in both commercial and extended temper- atures and a small footprint package to meet board space constraint requirements. device operation the sst34hf1621/1641 uses bes1#, bes2 and bef# to control operation of either the flash or the sram memory bank. when bef# is low, the flash bank is activated for read, program or erase operation. when bes1# is low, and bes2 is high the sram is activated for read and write operation. bef# and bes1# cannot be at low level, and bes2 cannot be at high level at the same time. if all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. all address, data, and control lines are shared by flash and sram memory banks which minimizes power consumption and loading. the device goes into standby when bef# and bes1# bank enables are raised to v ihc (logic high) or when bef# is high and bes2 is low. concurrent read/write operation dual bank architecture of sst34hf1621/1641 devices allows the concurrent read/write operation whereby the user can read from one bank while program or erase in the other bank. this operation can be used when the user needs to read system code in one bank while updating data in the other bank. see figure 1 for dual-bank memory organization. note: for the purposes of this table, write means to block-, sector, or chip-erase, or word-program as applicable to the appropriate bank. flash read operation the read operation of the sst34hf1621/1641 is controlled by bef# and oe#, both have to be low for the system to obtain data from the outputs. bef# is used for device selection. when bef# is high, the chip is deselected and only standby power is con- sumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either bef# or oe# is high. refer to the read cycle timing diagram for further details (figure 6). flash word-program operation the sst34hf1621/1641 are programmed on a word-by- word basis. before program operations, the memory must be erased first. the program operation consists of three steps. the first step is the three-byte load sequence for software data protection. the second step is to load word address and word data. during the word-program opera- tion, the addresses are latched on the falling edge of either bef# or we#, whichever occurs last. the data is latched on the rising edge of either bef# or we#, whichever occurs first. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or bef#, whichever occurs first. the program operation, once initiated, will be completed typically within 10 s. see fig- ures 7 and 8 for we# and bef# controlled program opera- tion timing diagrams and figure 21 for flowcharts. during the program operation, the only valid reads are data# poll- ing and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands issued during the internal program operation are ignored. c oncurrent r ead /w rite s tate t able flash sram bank 1 bank 2 read write no operation write read no operation write no operation read no operation write read write no operation write no operation write write
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 3 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 flash sector/block-erase operation the sector/block-erase operation allows the system to erase the device on a sector-by-sector or block-by-block basis. the sst34hf1621/1641 offer both sector-erase and block-erase mode. the sector architecture is based on uniform sector size of 1 kword. the block-erase mode is based on uniform block size of 32 kword. the sector- erase operation is initiated by executing a six-byte com- mand sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by executing a six-byte command sequence with block-erase command (50h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. see figures 12 and 13 for timing waveforms. any commands issued during the sector- or block-erase operation are ignored. flash chip-erase operation the sst34hf1621/1641 provide a chip-erase operation, which allows the user to erase all unprotected sectors/ blocks to the ?1? state. this is useful when the device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or bef#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 4 for the command sequence, figure 11 for timing diagram, and figure 24 for the flowchart. any commands issued dur- ing the chip-erase operation are ignored. flash write operation status detection the sst34hf1621/1641 provide one hardware and two software means to detect the completion of a write (pro- gram or erase) cycle, in order to optimize the system write cycle time. the hardware detection uses the ready/busy# (ry/by#) pin. the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a ready/busy# (ry/ by#), data# polling (dq 7 ) or toggle bit (dq 6 ) read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. ready/busy# (ry/by#) the sst34hf1621/1641 includes a ready/busy# (ry/ by#) output signal. ry/by# is actively pulled low during internal program/erase operation. the status of ry/by# is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or bank-erase, the ry/by# is valid after the rising edge of sixth we# or (ce#) pulse. ry/by# is an open drain output that allows several devices to be tied in parallel to v dd via an external pull up resistor. ready/busy# is in high impedance whenever oe# or ce# is high or rst# is low. flash data# polling (dq 7 ) when the sst34hf1621/1641 are in the internal program operation, any attempt to read dq 7 will produce the com- plement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during internal erase opera- tion, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling (dq 7 ) is valid after the rising edge of fourth we# (or bef#) pulse for program operation. for sector-, block- or chip-erase, the data# polling (dq 7 ) is valid after the rising edge of sixth we# (or bef#) pulse. after the completion of a program operation, data# polling on dq 7 remains active and the device may not return to the read mode for approximately 1 s. see figure 9 for data# polling (dq 7 ) timing diagram and figure 22 for a flowchart. flash toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. after the completion of a program operation, dq 6 will stop toggling for approximately 1 s. the device is then ready for the next operation. the toggle bit (dq 6 ) is valid after the rising edge of fourth we# (or bef#) pulse for program operation. for sector-, block- or chip-erase, the
4 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 to g g l e b i t ( d q 6 ) is valid after the rising edge of sixth we# (or bef#) pulse. see figure 10 for toggle bit timing dia- gram and figure 22 for a flowchart. data protection the sst34hf1621/1641 provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or bef# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, bef# high, or we# high will inhibit the write operation. this prevents inadvert- ent writes during power-up or power-down. hardware bloc k protection the sst34hf1621/1641 provide a hardware block protec- tion which protects the outermost 4 kword in the larger bank.the block is protected when wp# is held low. see figure 1 for block-protection location. a user can disable block protection by driving wp# high thus allowing erase or program of data into the protected sectors. wp# must be held high prior to issuing the write command and remain stable until after the entire write operation has completed. hardware reset (rst#) the rst# pin provides a hardware method of resetting the device to read array data. when the rst# pin is held low for at least t rp, any in-progress operation will terminate and return to read mode (see figure 18). when no internal program/erase operation is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place (see figure 17). the erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. software data protection (sdp) the sst34hf1621/1641 provide the jedec standard software data protection scheme for all data alteration operations, i.e., program and erase. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. the sst34hf1621/1641 are shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. dur- ing sdp command sequence, invalid commands will abort the device to read mode within t rc. the contents of dq 15 - dq 8 are ?don?t care? during any sdp command sequence. common flash memory interface (cfi) the sst34hf1621/1641 also contain the cfi information to describe the characteristics of the device. in order to enter the cfi query mode, the system must write three- byte sequence, same as software id entry command with 98h (cfi query command) to address 555h in the last byte sequence. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 5 through 7. the system must write the cfi exit command to return to read mode from the cfi query mode. product identification the product identification mode identifies the devices as the sst34hf1621/1641 and manufacturer as sst. this mode may be accessed by software operations only. the hardware device id read operation, which is typically used by programmers cannot be used on this device because of the shared lines between flash and sram in the multi-chip package. therefore, application of high voltage to pin a 9 may damage this device. users may use the software product identification operation to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see tables 3 and 4 for soft- ware operation, figure 14 for the software id entry and read timing diagram and figure 23 for the id entry com- mand sequence flowchart. table 1: p roduct i dentification address data manufacturer?s id 0000h 00bfh device id sst34hf1621 0001h 2761h sst34hf1641 0001h 2761h t1.2 523
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 5 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 product identification mode exit/ cfi mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. please note that the software id exit/ cfi exit command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 16 for timing waveform and figure 23 for a flowchart. sram operation with bes1# low, bes2 and bef# high, the sst34hf162x operates as 256k x8 or 128k x16 cmos sram, and the sst34hf164x operates as 512k x8 or 256k x16 cmos sram, with fully static operation requir- ing no external clocks or timing strobes. the cios pin configures the sram for x8 or x16 sram operation modes. the sst34hf162x sram is mapped into the first 256 kbyte/128 kword address space of the device, and the sst34hf164x sram is mapped into the first 512 kbyte/256 kword address space. when bes1#, bef# are high and bes2 is low, all memory banks are deselected and the device enters standby. read and write cycle times are equal. the control signals ubs# and lbs# provide access to the upper data byte and lower data byte. see table 3 for sram read and write data byte control modes of operation. sram read the sram read operation of the sst34hf1621/1641 is controlled by oe# and bes1#, both have to be low with we# and bes2 high for the system to obtain data from the outputs. bes1# and bes2 are used for sram bank selec- tion. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to the read cycle timing diagram, figure 3, for further details. sram write the sram write operation of the sst34hf1621/1641 is controlled by we# and bes1#, both have to be low, bes2 have to be high for the system to write to the sram. during the word-write operation, the addresses and data are ref- erenced to the rising edge of either bes1#, we#, or the falling edge of bes2 whichever occurs first. the write time is measured from the last falling edge of bes#1 or we# or the rising edge of bes2 to the first rising edge of bes1#, or we# or the falling edge of bes2. refer to the write cycle timing diagram, figures 4 and 5, for further details. 523 ill b1.1 superflash memory (bank 1) i/o buffers superflash memory (bank 2) 2 mbit or 4 mbit sram a ms - a 0 dq 15 - dq 8 dq 7 - dq 0 a ms = most significant address bef# wp# sa lbs# ubs# we# oe# bes1# bes2 cios control logic rst# ry/by# address buffers address buffers f unctional b lock d iagram
6 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 figure 1: sst34hf1621/1641, 1 m bit x 16 c oncurrent s uper f lash d ual -b ank m emory o rganization fffffh f8000h block 31 f7fffh f0000h block 30 effffh e8000h block 29 e7fffh e0000h block 28 dffffh d8000h block 27 d7fffh d0000h block 26 cffffh c8000h block 25 c7fffh c0000h block 24 bank 2 bffffh b8000h block 23 b7fffh b0000h block 22 affffh a8000h block 21 a7fffh a0000h block 20 9ffffh 98000h block 19 97fffh 90000h block 18 8ffffh 88000h block 17 87fffh 80000h block 16 7ffffh 78000h block 15 77fffh 70000h block 14 6ffffh 68000h block 13 67fffh 60000h block 12 5ffffh 58000h block 11 57fffh 50000h block 10 4ffffh 48000h block 9 47fffh 40000h block 8 3ffffh 38000h block 7 37fffh 30000h block 6 2ffffh 28000h block 5 27fffh 20000h block 4 1ffffh 18000h block 3 17fffh 10000h block 2 00ffffh 008000h block 1 007fffh 000fffh 000000h block 0 bank 1 bottom sector protection; 32 kword blocks; 1 kword sectors 4 kword sector protection (four 1 kword sectors) 523 ill f02.1 001000h
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 7 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 figure 2: p in a ssignments for 56- ball lfbga (8 mm x 10 mm ) c ombo m emory p inout table 2: p in d escription symbol pin name functions a ms 1 to a 0 1. a ms = most significant address address inputs to provide flash address, a 19 -a 0 . to provide sram address, a 16 -a 0 for 2m and a 17 -a 0 for 4m sa address input (sram) to provide sram address input in byte mode (x8). when cios is v il , the sram is in byte mode and sa provides the most significant address input. when cios is v ih , the sram is in word mode and sa becomes a don?t care pin. dq 15 -dq 0 data inputs/outputs to output data during read cycles and receive input data during write cycles. data is internally latched during a flash erase/program cycle. the outputs are in tri-state when oe# is high or bes1# is high or bes2 is low and bef# is high. bef# flash memory bank enable to activate the flash memory bank when bef# is low bes1# sram memory bank enable to activate the sram memory bank when bes1# is low bes2 sram memory bank enable to activate the sram memory bank when bes2 is high oe# output enable to gate the data output buffers we# write enable to control the write operations ubs# upper byte control (sram) to enable dq 15 -dq 8 lbs# lower byte control (sram) to enable dq 7 -dq 0 cios i/o configuration (sram) cios = v ih is word mode (x16), cios = v il is byte mode (x8) wp# write protect to protect and unprotect sectors from erase or program operation rst# reset to reset and return the device to read mode ry/by# ready/busy# to output the status of a program or erase operation ry/by# is a open drain output, so a 10k ? - 100k ? pull-up resistor is required to allow ry/by# to transition high indicating the device is ready to read. v ss ground v dd f power supply (flash) 2.7-3.3v power supply to flash only v dd s power supply (sram) 2.7-3.3v power supply to sram only nc no connection unconnected pins t2.5 523 523 56-lfbga ill p01.2 a11 a8 we# wp# lbs# a7 a15 a12 a19 bes2 rst# ubs# a6 a3 nc a13 a9 nc ry/by# a18 a5 a2 nc a14 a10 a17 a4 a1 a16 sa dq6 dq1 v ss a0 nc dq15 dq13 dq4 dq3 dq9 oe# bef# v ss dq7 dq12 v dds v ddf dq10 dq0 bes1# dq14 dq5 cios dq11 dq2 dq8 a b c d e f g h sst34hf1621/1641 8 7 6 5 4 3 2 1 top view (balls facing down)
8 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 table 3: o perational m odes s election 1 mode bef# bes1# bes2 2 cios 3 oe# we# sa lbs# ubs# dq 0-7 dq 8-15 full standby v ih v ih x xxxxxxhigh-zhigh-z xv il xxxxxx output disable v ih v il v ih xv ih v ih x x x high-z high-z v il v ih v ih xxxv ih v ih v il v ih xxv ih v ih x x x high-z high-z xv il flash read v il v ih xxv il v ih xxxd out d out xv il flash write v il v ih x x v ih v il xxxd in d in xv il flash erase v il v ih xx v ih v il xxx x x xv il sram read v ih v il v ih v ih v il v ih xv il v il d out d out v ih v il high-z d out v il v ih d out high-z v ih v il v ih v il v il v ih sa x x d out high-z sram write v ih v il v ih v ih xv il xv il v il d in d in v ih v il high-z d in v il v ih d in high-z v ih v il v ih v il xv il sa x x d in high-z product identification 4 v il v ih x x v il v ih x x x manufacturer?s id 5 device id 5 xv il t3.6 523 1. x can be v il or v ih , but no other value. 2. do not apply bef# = v il , bes1# = v il and bes2 = v ih at the same time 3. sram i/o configuration input cios; v ih = x16 (word mode), v il = x8 (byte mode) 4. software mode only 5. with a 19 -a 1 = 0; sst manufacturer?s id = 00bfh, is read with a 0 = 0, sst34hf1621/1641 device id = 2761h, is read with a 0 = 1
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 9 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 table 4: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 5555h aah 2aaah 55h 5555h a0h wa 3 data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 4 30h block-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba x 4 50h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 5 5555h aah 2aaah 55h 5555h 90h cfi query entry 5 5555h aah 2aaah 55h 5555h 98h software id exit/ cfi exit 6 5555h aah 2aaah 55h 5555h f0h t4.4 523 1. address format a 14 -a 0 (hex),address a 15- a 19 can be v il or v ih , but no other value, for the command sequence. 2. data format dq 15 -dq 8 can be v il or v ih , but no other value, for command sequence. 3. wa = program word address 4. sa x for sector-erase; uses a 19 -a 11 address lines ba x for block-erase; uses a 19 -a 15 address lines 5. the device does not remain in software product identification mode if powered down. 6. with a 20 -a 1 = 0; sst manufacturer?s id = 00bfh, is read with a 0 = 0 sst34hf1621/1641 device id = 2761h, is read with a 0 = 1. table 5: cfi q uery i dentification s tring 1 1. refer to cfi publication 100 for more details. address data data 10h 0051h query unique ascii string ?qry? 11h 0052h 12h 0059h 13h 0001h primary oem command set 14h 0007h 15h 0000h address for primary extended table 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h t5.0 523
10 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 table 6: s ystem i nterface i nformation address data data 1bh 0027h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min (00h = no v pp pin) 1eh 0000h v pp max (00h = no v pp pin) 1fh 0004h typical time out for word-program 2 n s (24 = 16 s) 20h 0000h typical time out for min size buffer program 2 n s (00h = not supported) 21h 0004h typical time out for individual sector/block-erase 2 n ms (2 4 = 16 ms) 22h 0006h typical time out for chip-erase 2 n ms (2 6 = 64 ms) 23h 0001h maximum time out for word-program 2 n times typical (2 1 x 2 4 = 32 s) 24h 0000h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual sector/block-erase 2 n times typical (2 1 x 2 4 = 32 ms) 26h 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 6 = 128 ms) t6.0 523 table 7: d evice g eometry i nformation address data data 27h 0015h device size = 2 n byte (15h = 21; 2 21 = 2m bytes) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of byte in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase sector/block sizes supported by device 2dh 00ffh sector information (y + 1 = number of sectors; z x 256b = sector size) 2eh 0003h y = 1023 + 1 = 1024 sectors (03ff = 1023) 2fh 0008h 30h 0000h z = 8 x 256 bytes = 2 kbyte/sector (0008h = 8) 31h 001fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y = 31 + 1 = 32 blocks (001f = 31) 33h 0000h 34h 0001h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) t7.0 523
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 11 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +125c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to v dd 1 +0.3v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd 1 +1.0v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240c output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. v dd = v ddf and v dds 2. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange range ambient temp v dd commercial 0c to +70c 2.7-3.3v extended -20c to +85c 2.7-3.3v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 19 and 20
12 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 table 8: dc o perating c haracteristics (v dd = v ddf and v dds = 2.7-3.3v) symbol parameter limits test conditions min max units i dd active v dd current address input=v il /v ih , at f=1/t rc min, v dd =v dd max, all dqs open read oe#=v il , we#=v ih flash 35 ma bef#=v il , bes1#=v ih , or bes2=v il sram 20 ma bef#=v ih , bes1#=v il , bes2=v ih concurrent operation 60 ma bef#=v ih , bes1#=v il , bes2=v ih write 1 flash 40 ma bef#=v il , bes1#=v ih , or bes2=v il , oe#=v ih sram 20 ma bef#=v ih , bes1#=v il , bes2=v ih i sb standby v dd current 3.0v 3.3v 40 75 a a v dd = v dd max, bef#=bes1#=v ihc , bes2=v ilc i alp i rt auto low power mode 3.0v 3.3v reset v dd current 40 75 30 a a a v dd =v dd max, bef#=v ilc , we#=v ihc , all i/o=v ilc /v ihc reset=v ss 0.3v i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7 v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v olf flash output low voltage 0.2 v i ol =100 a, v dd =v dd min v ohf flash output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min v ols sram output low voltage 0.4 v iol =1 ma, v dd =v dd min v ohs sram output high voltage 2.2 v ioh =-500 a, v dd =v dd min t8.6 523 1. i dd active while erase or program is in progress.
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 13 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 table 9: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t9.1 523 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. table 10: c apacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t10.0 523 table 11: f lash r eliability c haracteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t11.1 523
14 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 ac characteristics table 12: sram r ead c ycle t iming p arameters symbol parameter sst34hf1621/1641-70 sst34hf1621/1641-90 units min max min max t rcs read cycle time 70 90 ns t aas address access time 70 90 ns t bes bank enable access time 70 90 ns t oes output enable access time 35 45 ns t byes ubs#, lbs# access time 70 90 ns t blzs 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. bes# to active output 0 0 ns t olzs 1 output enable to active output 0 0 ns t bylzs 1 ubs#, lbs# to active output 0 0 ns t bhzs 1 bes# to high-z output 25 35 ns t ohzs 1 output disable to high-z output 25 35 ns t byhzs 1 ubs#, lbs# to high-z output 35 45 ns t ohs output hold from address change 10 10 ns t12.3 523 table 13: sram w rite c ycle t iming p arameters symbol parameter sst34hf1621/1641-70 sst34hf1621/1641-90 units min max min max t wcs write cycle time 70 90 ns t bws bank enable to end-of-write 60 80 ns t aws address valid to end-of-write 60 80 ns t asts address set-up time 0 0 ns t wps write pulse width 60 80 ns t wrs write recovery time 0 0 ns t byws ubs#, lbs# to end-of-write 60 80 ns t odws output disable from we# low 30 40 ns t oews output enable from we# high 0 0 ns t dss data set-up time 30 40 ns t dhs data hold from write time 0 0 ns t13.3 523
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 15 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 table 14: f lash r ead c ycle t iming p arameters v dd = 2.7-3.3v symbol parameter sst34hf1621/1641-70 sst34hf1621/1641-90 units minmaxminmax t rc read cycle time 70 90 ns t ce chip enable access time 70 90 ns t aa address access time 70 90 ns t oe output enable access time 35 45 ns t clz 1 bef# low to active output 0 0 ns t olz 1 oe# low to active output 0 0 ns t chz 1 bef# high to high-z output 20 30 ns t ohz 1 oe# high to high-z output 20 30 ns t oh 1 output hold from address change 0 0 ns t rp 1 rst# pulse width 500 500 ns t rhr 1 rst# high before read 50 50 ns t ry 1,2 rst# pin low to read 150 150 s t14.4 523 1. this parameter is measured only for init ial qualification and after the design or pr ocess change that could affect this param eter. 2. this parameter applies to sector-erase and block-erase operations. this parameter does not apply to chip-erase operations. table 15: f lash p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp word-program time 20 s t as address setup time 0 ns t ah address hold time 40 ns t cs we# and bef# setup time 0 ns t ch we# and bef# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp bef# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for initial qualification and a fter a design or process change that could affect this paramet er. we# pulse width high 30 ns t cph 1 bef# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t by 1 ry/by# delay time 90 ns t br bus recovery time 1 s t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 100 ms t15.3 523
16 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 figure 3: sram r ead c ycle t iming d iagram figure 4: sram w rite c ycle t iming d iagram (we# c ontrolled ) 1 addresses a mss-0 dq 15-0 ubs#, lbs# a mss = most significant sram address oe# bes1# bes2 t rcs t aas t bes t oes t blzs t olzs t byes t bylzs t byhzs data valid t ohzs t bhzs t ohs 523 ill f15.0 t bes t aws addresses a mss-0 bes1# bes2 we# ubs#, lbs# notes: 1. if oe# is high during the write cycle, the outputs will remain at high impedance. 2. if bes1# goes low or bes2 goes high coincident with or after we# goes low, the output will remain at high impedance. if bes1# goes high or bes2 goes low coincident with or before we# goes high, the output will remain at high impedance. because din signals may be in the output state at this time, input signals of reverse polarity must not be applied. t wps t wrs t wcs t asts t bws t bws t byws t odws t oews t dss t dhs 523 ill f16.2 note 2 note 2 dq 15-8, dq 7-0 valid data in
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 17 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 figure 5: sram w rite c ycle t iming d iagram (ubs#, lbs# c ontrolled ) 1 addresses a mss-0 we# bes1# bes2 t bws t bws t aws t wcs t wps t wrs t asts t byws dq 15-8, dq 7-0 valid data in note 2 note 2 t dss t dhs ubs#, lbs# notes: 1. if oe# is high during the write cycle, the outputs will remain at high impedance. 2. because din signals may be in the output state at this time, input signals of reverse polarity must not be applied. 523 ill f18.0
18 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 figure 6: f lash r ead c ycle t iming d iagram figure 7: f lash we# c ontrolled w ord -p rogram c ycle t iming d iagram 523 ill f04.0 address a 19-0 dq 15-0 we# oe# bef# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 523 ill f05.3 address a 19-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs t by bef# ry/by# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data word (addr/data) oe# we# t br t bp note: x can be v il or v ih , but no other value. valid
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 19 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 figure 8: f lash bef# c ontrolled w ord -p rogram c ycle t iming d iagram figure 9: f lash d ata # p olling t iming d iagram valid 523 ill f06.3 address a 19-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data word (addr/data) oe# bef# t bp t by ry/by# t br note: x can be v il or v ih , but no other value. 523 ill f07.2 address a 19-0 dq 7 data# data# valid data we# oe# bef# t oeh t oe t ce t oes t br
20 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 figure 10: f lash t oggle b it t iming d iagram figure 11: f lash we# c ontrolled c hip -e rase t iming d iagram 523 ill f08.2 address a 19-0 dq 6 we# oe# bef# t oe t oeh t ce two read cycles with same outputs valid data t br valid t br 523 ill f09.5 address a 19-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx10 xx55 xxaa xx80 xxaa 5555 oe# bef# six-byte code for chip-erase t sce t wp note: this device also supports bef# controlled chip-erase operation. the we# and bef# signals are interchageable as long as minimum timings are met. (see table 15) x can be v il or v ih , but no other value. t by ry/by#
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 21 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 figure 12: f lash we# c ontrolled b lock -e rase t iming d iagram figure 13: f lash we# c ontrolled s ector -e rase t iming d iagram 523 ill f10.4 address a 19-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# bef# six-byte code for block-erase t wp note: this device also supports bef# controlled block-erase operation. the we# and bef# signals are interchageable as long as minimum timings are met. (see table 15) ba x = block address x can be v il or v ih , but no other value. t by ry/by# valid t br t be 523 ill f11.4 address a 19-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# bef# six-byte code for sector-erase t se t wp note: this device also supports bef# controlled sector-erase operation. the we# and bef# signals are interchageable as long as minimum timings are met. (see table 15) sa x = sector address x can be v il or v ih , but no other value. t by ry/by# valid t br
22 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 figure 14: f lash s oftware id e ntry and r ead figure 15: f lash cfi e ntry and r ead 523 ill f12.5 address a 14-0 t ida dq 15-0 we# sw0 sw1 device id = 2761h for sst34hf1621 and 2761h for sst34hf1641 note: x can be v il or v ih , but no other value sw2 5555 2aaa 5555 0000 0001 oe# bef# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 523 ill f13.1 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 oe# bef# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx98 note: x can be v il or v ih , but no other value.
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 23 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 figure 16: f lash s oftware id e xit /cfi e xit figure 17: rst# t iming ( when no internal operation is in progress ) figure 18: rst# t iming ( during s ector - or b lock -e rase operation ) 523 ill f14.2 address a 14-0 dq 15-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# bef# xxaa xx55 xxf0 note: x can be vil or vih, but no other value 523 ill f29.0 ry/by# 0v rst# ce#/oe# t rp t rhr 523 ill f30.0 ry/by# ce# oe# t rp t ry t br rst#
24 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 figure 19: ac i nput /o utput r eference w aveforms figure 20: a t est l oad e xample 523 ill f19.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 523 ill f20.0 to tester to dut c l
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 25 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 figure 21: w ord -p rogram a lgorithm 523 ill f21.4 start load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xxa0h address: 5555h load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih, but no other value.
26 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 figure 22: w ait o ptions 523 ill f22.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 27 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 figure 23: s oftware p roduct id/cfi c ommand f lowcharts 523 ill f23.3 load data: xxaah address: 5555h software product id entry command sequence load data: xx55h address: 2aaah load data: xx90h address: 5555h wait t ida read software id load data: xxaah address: 5555h cfi query entry command sequence load data: xx55h address: 2aaah load data: xx98h address: 5555h wait t ida read cfi data load data: xxaah address: 5555h software id exit/cfi exit command sequence load data: xx55h address: 2aaah load data: xxf0h address: 5555h wait t ida return to normal operation note: x can be v il or v ih, but no other value.
28 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 figure 24: e rase c ommand s equence 523 ill f24.2 load data: xxaah address: 5555h chip-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx10h address: 5555h load data: xxaah address: 5555h wait t sce chip erased to ffffh load data: xxaah address: 5555h sector-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx30h address: sa x load data: xxaah address: 5555h wait t se sector erased to ffffh load data: xxaah address: 5555h block-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx50h address: ba x load data: xxaah address: 5555h wait t be block erased to ffffh note: x can be v il or v ih, but no other value.
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 29 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 product ordering information valid combinations for sst34hf1621 sst34hf1621-70-4c-lfp sst34hf1621-70-4c-l1p sst34hf1621-90-4c-lfp sst34hf1621-90-4c-l1p sst34hf1621-70-4e-lfp sst34hf1621-70-4e-l1p sst34hf1621-90-4e-lfp sst34hf1621-90-4e-l1p valid combinations for sst34hf1641 sst34hf1641-70-4c-lfp sst34hf1641-70-4c-l1p sst34hf1641-90-4c-lfp sst34hf1641-90-4c-l1p sst34hf1641-70-4e-lfp sst34hf1641-70-4e-l1p sst34hf1641-90-4e-lfp sst34hf1641-90-4e-l1p note: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations. device speed suffix1 suffix2 sst34h f16 x x -xxx -x x -x x package modifier p = 56 balls package type lf = lfbga (8mm x 10mm x 1.4mm, 0.4mm ball size) l1 = lfbga (8mm x 10mm x 1.4mm, 0.45mm ball size) temperature range c = commercial = 0c to +70c e = extended = -20c to +85c minimum endurance 4 =10,000 cycles read access speed 70 = 70 ns 90 = 90 ns bank split 1 = 12m + 4m sram density 0 = no sram 2 = 2 mbit 4 = 4 mbit flash density 16 = 16 mbit voltag e h = 2.7-3.3v
30 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 packaging diagrams 56- ball l ow - profile , f ine - pitch b all g rid a rray (lfbga) 8 mm x 10 mm (64 possible ball positions ) sst p ackage c ode : lfp note: this package will be replaced by l1p which increases the ball size from 400-micron to 450-micron. check with factory for migration schedule. a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 8 7 6 5 4 3 2 1 seating plane 0.32 0.05 1.30 0.10 0.15 8.00 0.20 0.40 0.05 (56x) a1 corner 10.00 0.20 0.80 5.60 0.80 5.60 56ba-lfbga-lfp-8x10-400mic-ill.6 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registered. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.1 (.05) mm. 4. the actual shape of the corners may be slightly different than as portrayed in the drawing. 8 7 6 5 4 3 2 1 1mm
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 31 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 56- ball l ow - profile , f ine - pitch b all g rid a rray (lfbga) 8 mm x 10 mm (64 possible ball positions ) sst p ackage c ode : l1p a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 8 7 6 5 4 3 2 1 seating plane 0.35 0.05 1.30 0.10 0.15 8.00 0.20 0.45 0.05 (56x) a1 corner 10.00 0.20 0.80 5.60 0.80 5.60 56ba-lfbga-l1p-8x10-450mic-ill.1 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registered. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.1 (.05) mm. 4. the actual shape of the corners may be slightly different than as portrayed in the drawing. 8 7 6 5 4 3 2 1 1mm
32 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory sst34hf1621 / sst34hf1641 ?2001 silicon storage technology, inc. s71172-05-000 10/01 523 silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.ssti.com

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